Various prior art optical detection arrangements are disclosed in U.S. Pat. Nos. 3,478,220, 3,704,396, 3,742,222, 3,746,863, 3,764,813, 3,860,754, 3,970,846, 4,122,438, 4,198,623, 4,205,304, 4,245,244, 4,266,124, 4,267,443, 4,301,447, 4,313,109, 4,384,201, 4,563,578, 4,585,940, 4,591,710 and others.
Among these prior art technologies, U.S. Pat. Nos. 4,245,244, 4,585,940 and some others are configured to prevent erroneous operation caused by external light.
A conventional type of optical coordinate system input device which is affected by external light is described in general below and with reference to FIG. 4.
An optical coordinate system input device in general is disposed at the front face of a CRT display, LCD or other image display apparatus and activated to supply a coordinate system instruction to a computer. A number of pairs of light emitting elements and light receptor elements are opposed to each other along the outer peripheral margins of the screen of the CRT display, etc., and the light emitting elements and light receptor elements are selectively scanned to detect any interruption of a light signal by an operators finger or other blocker during the scanning to obtain a coordinate system signal.
FIG. 4 is a circuit diagram of prior art optical coordinate system in which a number of light emitting diodes L1 through Ln are placed on two adjacent margins of the front face outer periphery of a CRT or other image display apparatus. Photo transistors PT1 through PTn, employed as the light receptor elements, are placed on the other two adjacent margins and opposed to the light emitting diodes L1 through Ln. Horizontally arranged pairs of light emitting diodes (L1 through Lm) and photo transistors (PT1 through PTm) form X axes of the coordinate system, and vertically arranged pairs of light emitting diodes (Lm+1 through Ln) and photo resistors (PTm+1 through PTn) form Y axes of the coordinate system. Cathodes of the light emitting diodes L1 through Ln and emitters of the photo transistors PT1 through PTn are all connected to ground. Anodes of the light emitting diodes L1 through Ln are connected to respective ends of normally opened switching elements SL1 through SLn which have the other ends connected in common to the emitter of a driving transistor Q1. Switching elements SL1 through SLn together form first switching circuit 1. The collectors of the photo transistors PT1 through PTn are connected to respective ends of normally opened switching elements S1 through Sn which have other ends connected in common to a waveform shaper 2. Switching elements S1 through Sn together form second switching circuit 3.
In the waveform shaper 2, a common junction p of the switching elements S1 through Sn is connected to the base of a transistor Q2 via a capacitor C1. The emitter of the transistor Q2 is connected to ground, and the collector thereof is connected to the driving power source V via series-connected resistors R1 and R2. A junction q of resistors R1 and R2 is connected to ground via a pulse bypass capacitor C2, and also connected to the common junction p of the switching elements S1 through Sn via a resistor R4. The base of the transistor Q2 is connected to the driving power source terminal V via a resistor R5.
An output from the waveform shaping circuit 2 is applied to an amplifier 4 through the collector of the transistor Q2, adequately amplified there and subsequently applied to a microprocessor (hereinafter called CPU) 5.
The CPU 5 applies a switching signal a to first and second switching circuits 1 and 3 to sequentially switch switching elements SL1 through SLn and S1 through Sn to sequentially sample the light transmitted between opposing phototransistor/light emitting diode pairs. Additionally, the CPU 5 applies a driving signal b to the base of the driving transistor Q1 which, in response to this, provides three or more current pulses through each of the light emitting diodes L1 through Ln as each opposing pair of the light emitting diodes L1 through Ln and photo transistors PT1 through PTn is selected by CPU 5. Thereby, a selected one of the light emitting diode L1 through Ln emits several pulsating flashes of light. The collector of the driving transistor Q1 is connected to the driving power source terminal V via an appropriate resistor.
With this arrangement, a voltage exists at junction p which is determined by the driving power source terminal V divided by the resistors R1 and R4 in series with the impedance of a selected one of photo transistors PT1 through PTn. If the voltage at the junction p does not change, the transistor Q2 is in conduction, and no output is applied to the amplifier circuit 4.
When a selected one of the photo transistors PT1 through PTn receives pulsating light signals produced by a selected one of the light emitting diodes L1 through Ln, the impedance of the photo transistor decreases due to the light reception, and the divided voltage at the junction p decreases with the impedance of the phototransistor. Therefore, the transistor Q2 is pulsatingly conductive or nonconducted and applies a pulsating output to the amplifier circuit 4.
If the light emitted from light emitting diodes L1 through Ln is not blocked by a finger or other obstacle, the repetitive pulse signals at the collector of transistor Q2 are supplied to amplifier circuit 4, amplified, and supplied to the CPU 5. In contrast, if the light signal is blocked, no repetitive pulse signal is supplied from the amplifier circuit 4 to the CPU 5. The CPU 5 is then able to calculate the x-y coordinates of a light blocking obstacle based on absence or presence of the repetitive pulse signal applied to the CPU 5.
In the above-described prior art optical coordinate system input device, the impedance of photo transistors PT1 through PTn decreases to a substantial saturated state upon entrance of strong external turbulent light, and the divided voltage at the junction p decreases responsively. As a result, with high ambient light, the impedance of the phototransistors PT1 through PTn can only decrease a small amount upon receipt of light signals from light emitting diodes L1 through Ln before becoming saturated. Therefore, the voltage change of the divided voltage at the junction p is too small to invert the transistor Q2 to non-conduction, and a false output is applied to the amplifier circuit 4. As a result, the CPU 5 erroneously judges that the light signal is blocked and an erroneous coordinate system signal is produced.